Design a VLSI Phase-Locked Loop (PLL) in 0.18µm TSMC CMOS process technology (Intel corporation).

Design a continuous-time Sigma-Delta ADC (NXP semiconductors ).

Design a fully differential 80MHZ 12bit RSD-based pipelined ADC (NXP semiconductors).

Design VLSI RX linear equalizer Circuits (Intel corporation).

Design an algorithmic of a Redundant Signed Digit based Pipelined ADC (NXP semiconductors).

Design of LNA and Mixer for a GSM Receiver in the TSMC 0.4µm technology.

Implemented and Analyzed the test cost reduction techniques for Mixed Signal/ RF circuits: Including Artificial Neural Network, Periodic update, adaptive test method.

Design, layout, fabrication, and characterization of sensors and data converters in a 0.18µm CMOS technology (IBM corporation).